Many data systems now involve the use of more than one data processor and a common memory which is desirably simultaneously accessed by more than one processor. Such simultaneous access is not, however, possible. The processors are said to be in contention for memory. Therefore the processors must wait their turn. If an earlier serviced processor requires a transfer in or out of a large amount of data, the wait for a subsequent processor will be intolerably long. The goal is a contention-free system wherein each processor at any time can have access to the memory.
FIG. 1 illustrates a prior art step toward a contention-free system. In FIG. 1 there are, by way of example, four data buses (each of 32 wires in a 32 bit system) forming a data transfer network, four processors each coupled to a different data bus and four memories, each switchably connected to all the data buses. An open circle on a bus represents a 32 pole single throw data switch controlled by control means not shown. In operation of the exemplary system, each processor is typically connected with an associated memory, but there are still times when two or more processors simultaneously want to connect with one memory. Further, although the number 32 is a realistic number of bits a realistic system may have 8 or more processors, memories and data buses. Thus the data transfer network involves at least 8.times.8=64 32 pole switches and at least 8.times.8.times.32=2048 connections making it a very complex device. In spite of the complexity, the goal of the contention-free memory access is still not met as more than one processor may want information from the same memory at the same time.
Bit sliced memory arrangements are known. In a bit sliced memory arrangement there are as many memories as there are bits in a word. Thus in a system involving a 32-bit word there are 32 memories each coupled to every processor. Such a system requires a separate control bus to transfer address and control signals between the various processors and the various memories. The bit slice system involves less complexity than the illustrated prior art system of FIG. 1 but is worse in the sense that only one processor can connect with the memory at one time.